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LTC2923 1 2923fa flexible power supply tracking tracks both up and down power supply sequencing supply stability is not affected controls two supplies without series fets controls a third supply with a series fet adjustable ramp rates electronic circuit breaker available in 10-lead ms and 12-lead (4mm 3mm) dfn packages power supply tracking controller v core and v i/o supply tracking microprocessor, dsp and fpga supplies servers communication systems the ltc ? 2923 provides a simple solution to power supply tracking and sequencing requirements. by selecting a few resistors, the supplies can be configured to ramp-up and ramp-down together or with voltage offsets, time delays or different ramp rates. by introducing currents into the feedback nodes of two independent switching regulators, the LTC2923 causes their outputs to track without inserting any pass element losses. because the currents are controlled in an open- loop manner, the LTC2923 does not affect the transient response or stability of the supplies. furthermore, it presents a high impedance when power-up is complete, effectively removing it from the dc/dc circuit. for systems that require a third supply, one supply can be controlled with a series fet. this optional series fet can also control a supply that does not allow direct access to its feedback resistors (e.g., a power module) or a supply whose output cannot be forced to ground (e.g., a 3-termi- nal linear regulator). when the fet is used, an electronic circuit breaker provides protection from short-circuit conditions. q1 10nf v cc v in v in 138k v in 3.3v 16.5k 887k 35.7k 1.8v 3.3v 16.5k 412k 13k 100k on rampbuf track1 track2 fb1 gate LTC2923 gnd 2923 ta01 ramp 412k 2.5v 887k dc/dc in fb = 1.235v out dc/dc in fb = 0.8v out fb2 sdo status 1v/div 1ms/div 2923 ta02 3.3v 2.5v 1.8v 1v/div 3.3v 2.5v 1.8v 1ms/div 2923 f08b features descriptio u typical applicatio u applicatio s u , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. patents pending.
LTC2923 2 2923fa supply voltage (v cc ) ................................ C 0.3v to 10v input voltages on ........................................................ C 0.3v to 10v track1, track2 ...................... C 0.3v to v cc + 0.3v ramp ........................................... C 0.3v to v cc + 1v output voltages fb1, fb2, sdo, status ........................ C 0.3v to 10v rampbuf ................................. C 0.3v to v cc + 0.3v gate (note 2) ................................... C 0.3v to 11.5v (note 1) absolute axi u rati gs w ww u package/order i for atio uu w consult ltc marketing for parts specified with wider operating temperature ranges. ms part marking ltaed ltaee order part number t jmax = 125 c, ja = 120 c/w 1 2 3 4 5 v cc on track1 track2 rampbuf 10 9 8 7 6 ramp gate fb1 fb2 gnd top view ms package 10-lead plastic msop average current track1, track2 .............................................. 5ma fb1, fb2 ............................................................ 5ma rampbuf ......................................................... 5ma operating temperature range LTC2923c ............................................... 0 c to 70 c LTC2923i ............................................ C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec) ms package .................................................... 300 c de part marking 2923 order part number LTC2923cde LTC2923ide 12 11 10 9 8 7 1 2 3 4 5 6 ramp gate status sdo fb1 fb2 v cc on track1 track2 rampbuf gnd top view 13 de12 package 12-lead (4mm 3mm) plastic dfn t jmax = 125 c, ja = 43 c/w exposed pad (pin 13) internally connected to gnd (pcb connection optional) symbol parameter conditions min typ max units v cc input supply range 2.9 5.5 v i cc input supply current i fbx = 0, i trackx = 0 1.3 3 ma i fbx = C1ma, i trackx = C1ma, 5710 ma i rampbuf = C2ma v cc(uvl) input supply undervoltage lockout v cc rising 2.2 2.5 2.7 v ? v cc(uvlhyst) input supply undervoltage lockout hysteresis 25 mv ? v gate external n-channel gate drive (v gate C v cc )i gate = C1 a 5 5.5 6 v i gate gate pin current gate on, v gate = 0v, no faults C7 C10 C13 a gate off, v gate = 5v, no faults 7 10 13 a gate off, v gate = 5v, 5 20 50 ma short-circuit fault v on(th) on pin threshold voltage v on rising 1.212 1.230 1.248 v ? v on(hyst) on pin hysteresis 30 75 150 mv the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. 2.9v < v cc < 5.5v unless otherwise noted (note 3). electrical characteristics LTC2923cms LTC2923ims
LTC2923 3 2923fa symbol parameter conditions min typ max units v on(fc) on pin fault clear threshold voltage 0.3 0.4 0.5 v i on on pin input current v on = 1.2v, v cc = 5.5v 0 100 na ? v ds(th) fet drain-source overcurrent voltage threshold 160 200 240 mv (v cc C v ramp ) i ramp ramp pin input current 0v < ramp < v cc , v cc = 5.5v 0 1 a v rampbuf(ol) rampbuf low voltage i rampbuf = 2ma 90 150 mv v rampbuf(oh) rampbuf high voltage (v cc C v rampbuf )i rampbuf = C2ma 100 200 mv v os ramp buffer offset (v rampbuf C v ramp )v rampbuf = v cc /2, i rampbuf = 0a C30 0 30 mv i error(%) i fbx to i trackx current mismatch i trackx = C10 a 0 5% i error(%) = (i fbx C i trackx )/i trackx i trackx = C1ma 0 5% v trackx track pin voltage i trackx = C10 a 0.776 0.8 0.824 v i trackx = C1ma 0.776 0.8 0.824 v i fb(leak) i fb leakage current v fb = 1.5v, v cc = 5.5v 1 100 na v fb(clamp) v fb clamp voltage 1 a < i fb < 1ma 1.5 1.7 2 v v sdo(ol) sdo output low voltage i sdo = 3ma 0.2 0.4 v v status(ol) status output low voltage i status = 3ma 0.2 0.4 v t psc short-circuit propagation delay v ds high v ds = v cc , v cc = 2.9v 10 20 s to gate low the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. 2.9v < v cc < 5.5v unless otherwise noted (note 3). electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the gate pin is internally limited to a minimum of 11.5v. driving this pin to voltages beyond the clamp may damage the part. note 3: all currents into the device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. typical perfor a ce characteristics uw v gate vs v cc v gate vs i gate i gate vs v cc fast pull-down v cc (v) 2 8 v gate (v) 9 10 12 11 34 2923 g01 56 i gate ( a) 0 0 v gate (v) 5 10 15 510 v cc = 2.9v v cc = 5.5v 2923 g02 15 v cc (v) 0 0 i gate (ma) 5 10 15 20 30 1 234 2923 g03 56 25 v gate = 5v specifications are at t a = 25 c unless otherwise noted.
LTC2923 4 2923fa typical perfor a ce characteristics uw specifications are at t a = 25 c unless otherwise noted. i gate fast pull-down vs temperature temperature ( c) C50 i gate (ma) 15 20 25 25 75 2923 g04 10 5 0 C25 0 50 30 35 40 100 v cc = 5.5v v cc = 2.9v v cc (v) 2.5 3 i cc (ma) 1.3 1.4 1.5 5 2923 g05 1.2 1.1 1.0 3.5 4 4.5 5.5 i trackx = i fbx = 0ma i rampbuf = 0ma v cc (v) 2.5 3 i cc (ma) 7.8 7.9 8.0 5 2923 g06 7.7 7.6 7.5 3.5 4 4.5 5.5 i trackx = i fbx = C1ma i rampbuf = C2ma i cc vs v cc i cc vs v cc v trackx vs temperature v rampbuf(ol) vs temperature temperature ( c) C50 0.785 v trackx (v) 0.790 0.795 0.800 0.805 0.810 C25 02550 2923 g07 75 100 v cc = 2.9v i trackx = 1ma v cc = 2.9v i trackx = 10 a v cc = 5.5v i trackx = 1ma v cc = 5.5v i trackx = 10 a temperature ( c) C50 60 v rampbuf(ol) (mv) 70 80 90 100 120 C25 02550 2923 g08 75 100 110 v cc = 2.9v v cc = 5.5v v rampbuf(oh) vs temperature i trackx vs v cc temperature ( c) C50 130 120 110 100 90 80 70 60 25 75 2923 g09 C25 0 50 100 v rampbuf(oh) (mv) v cc = 2.9v v cc = 5.5v v cc (v) 3 i trackx (ma) 11 12 13 4.5 5.5 2923 g10 10 9 8 3.5 4 5 14 15 16 v trackx = 0v v cc (v) 0 0 v sdo(ol) (v) 0.2 0.2 0.6 0.8 1.0 1 234 2923 g11 5 i sdo = 10 a i sdo = 5ma v sdo(ol) vs v cc tracking cell error vs i trackx i trackx (ma) 0 error (%) 3 4 5 4 2923 g12 2 1 0 1 2 3 5 error = ? C 1 v trackx 0.8v i fbx i trackx exactly 2%
LTC2923 5 2923fa uu u pi fu ctio s v cc (pin 1): positive supply input pin. the operating supply input range is 2.9v to 5.5v. an undervoltage lockout circuit resets the part when the supply is below 2.5v. v cc should be bypassed to gnd with a 0.1 f capacitor. on (pin 2): on control input. the on pin has a threshold of 1.23v with 75mv of hysteresis. an active high will cause 10 a to flow from the gate pin, ramping up the supplies. an active low pulls 10 a from the gate pin, ramping the supplies down. pulling the on pin below 0.4v resets the electronic circuit breaker in the LTC2923. if a resistive divider connected to v cc drives the on pin, the supplies will automatically start up when v cc is fully powered. track1, track2 (pins 3, 4): tracking control input. a resistive voltage divider between rampbuf and trackx determines the tracking profile of a slave supply (see applications information). trackx pulls up to 0.8v and the current supplied at trackx is mirrored at fbx. trackx is capable of supplying at least 1ma when v cc = 2.9v. because a trackx pin is capable of supplying up to 30ma under short-circuit conditions, avoid connecting trackx to gnd for extended periods. limit the capacitance at each trackx pin to less than 25pf. float the trackx pins if unused. rampbuf (pin 5): ramp buffer output. provides a low impedance buffered version of the signal on the ramp pin. this buffered output drives the resistive dividers that connect to the trackx pins. limit the capacitance at the rampbuf pin to less than 100pf. gnd (pins 6, 13): circuit ground. fb1, fb2 (pins 8, 7): feedback control output. fbx pulls up on the feedback node of slave supplies. tracking is achieved by mirroring the current from trackx into fbx. if the appropriate resistive divider connects rampbuf and trackx, the fbx current will force outx to track ramp. to prevent damage to the slave supply, the fbx pin will not force the slaves feedback node above 1.7v. in addition, it will not actively sink current from this node even when the LTC2923 is unpowered. float the fb pins if unused. gate (pin 9/pin 11): gate drive for external n-channel fet. when the on pin is high, an internal 10 a current source charges the gate of the external n-channel mos- fet. a capacitor connected from gate to gnd sets the ramp rate. an internal charge pump guarantees that gate will pull up to 5v above v cc ensuring that logic level n-channel fets are fully enhanced. when the on pin is pulled low, the gate pin is pulled to gnd with a 10 a current source. under a short-circuit condition, the elec- tronic circuit breaker in the LTC2923 pulls the gate low immediately with 20ma. tie gate to gnd if unused. it is a good practice to add a 10 ? resistor between this capacitor and the fets gate to prevent high frequency fet oscillations. ramp (pin 10/pin 12): ramp buffer input. when the ramp pin is connected to the source of the external n-channel fet, the slave supplies track the fets source as it ramps up and down. if the gate is fully enhanced (gate > ramp + 4.9v) and (v cc C ramp > 200mv) indicates a shorted output, then the electronic circuit breaker trips and gate quickly pulls low with 20ma. the gate will not ramp up again until on is pulled below 0.4v and then above 1.23v. alternatively, when no external fet is used, the ramp pin can be tied directly to the gate pin. in this configuration, the supplies track the capacitor on the gate pin as it is charged and discharged by the 10 a current source controlled by the on pin. ramp must not be driven above v cc (except by the gate pin). sdo (pin 9, de package only): slave supply shutdown output. sdo is an open-drain output that holds the shut- down (run/ss) pins of the slave supplies low until the on pin is pulled above 1.23v. if the slave supply is capable of operating with an input supply that is lower than the LTC2923s minimum operating voltage of 2.9v, the sdo pin can be used to hold off the slave supplies. sdo will be pulled low again when ramp < 100mv and on < 1.23v. status (pin 10, de package only): power good status indicator. the status pin is an open-drain output that pulls low until gate has been fully charged at which time all supplies will have reached their final operating voltage. ms/de packages
LTC2923 6 2923fa uu w fu ctio al block diagra rampbuf fb2 track2 pin numbers in parentheses correspond to the 10-lead msop package gnd 0.8v v cc 2923 fbd 1 + C fb1 ramp gate (9) track1 0.8v v cc + C on v cc v cc 0.1v v cc 2.6v v cc v cc C ramp > 200mv v cc < 2.6v ramp < 100mv ramp > v cc short-circuit fault latch gate gate > ramp + 4.9v + C + C + C + C + C 10 a onsig 10 a charge pump rq q 0.4v 1.2v s 4.9v 0.2v 6 4 3 5 9 10 2 status sdo 1 8 7 onsig 11 (10) 12
LTC2923 7 2923fa applicatio s i for atio wu uu power supply tracking and sequencing the LTC2923 handles a variety of power-up profiles to satisfy the requirements of digital logic circuits including fpgas, plds, dsps and microprocessors. these require- ments fall into one of the four general categories illus- trated in figures 1 to 4. some applications require that the potential difference between two power supplies must never exceed a speci- fied voltage. this requirement applies during power-up and power-down as well as during steady-state operation, often to prevent destructive latch-up in a dual supply asic. typically, this is achieved by ramping the supplies up and down together (figure 1). in other applications it is desir- able to have the supplies ramp up and down with fixed voltage offsets between them (figure 2) or to have them ramp up and down ratiometrically (figure 3). certain applications require one supply to come up after another. for example, a system clock may need to start before a block of logic. in this case, the supplies are sequenced as in figure 4 where the 2.5v supply ramps up after the 1.8v supply is completely powered. operation the LTC2923 provides a simple solution to all of the power supply tracking and sequencing profiles shown in figures 1 to 4. a single LTC2923 controls up to three supplies with two slave supplies that track a master signal. with just two resistors, a slave supply is configured to ramp up as a function of the master signal. this master signal can be a third supply that is ramped up through an external fet, whose ramp rate is set with a single capacitor, or it can be a signal generated by tying the gate and ramp pins to an external capacitor. 1v/div 1ms/div 2923 f01 figure 1. coincident tracking 1v/div 1ms/div 2923 f02 figure 2. offset tracking 1v/div 1ms/div 2923 f03 figure 3. ratiometric tracking 1v/div 1ms/div 2923 f04 figure 4. supply sequencing master slave1 slave2 master slave1 slave2 master slave1 slave2 slave1 slave2
LTC2923 8 2923fa applicatio s i for atio wu uu tracking cell the LTC2923s operation is based on the tracking cell shown in figure 5, which uses a proprietary wide-range current mirror. the tracking cell shown in figure 5 servos the track pin at 0.8v. the current supplied by the track pin is mirrored at the fb pin to establish a voltage at the output of the slave supply. the slave output voltage varies with the master signal, enabling the slave supply to be controlled as a function of the master signal with terms set by r ta and r tb . by selecting appropriate values of r ta and r tb , it is possible to generate any of the profiles in figures 1 to 4. controlling the ramp-up and ramp-down behavior the operation of the LTC2923 is most easily understood by referring to the simplified functional diagram in fig- ure 6. when the on pin is low, the gate pin is pulled to ground causing the master signal to remain low. since the currents through r tb1 and r tb2 are at their maximum when the master signal is low, the currents from fb1 and fb2 are also at their maximum. these currents drive the slaves outputs to their minimum voltages. when the on pin rises above 1.23v, the master signal rises and the slave supplies track the master signal. the ramp rate is set by an external capacitor driven by a 10 a current source from an internal charge pump. if no exter- nal fet is used, the ramp rate is set by tying the ramp and gate pins together at one terminal of the external capaci- tor (see the ratiometric tracking example). in a properly designed system, when the master signal has reached its maximum voltage the current from the trackx pin is zero. in this case, there is no current from the fbx pin and the LTC2923 has no effect on the output voltage accuracy, transient response or stability of the slave supply. when the on pin falls below v on(th) C ? v on(hyst) , typi- cally 1.225v, the gate pin pulls down with 10 a and the master signal and the slave supplies will fall at the same rate as they rose previously. the on pin can be controlled by a digital i/o pin or it can be used to monitor an input supply. by connecting a resistive divider from an input supply to the on pin, the supplies will ramp up only after the monitored supply has reached a preset voltage. optional external fet the coincident tracking example (figures 8 and 9) illus- trates how an optional external n-channel fet can ramp up a single supply that becomes the master signal. when used, the fets gate is charged by the gate pin and its source is tied to the ramp pin. under normal operation, the gate pin sources or sinks 10 a to ramp the fets gate up or down at a rate set by the external capacitor con- nected to the gate pin. it is a good practice to add 10 ? between the fets gate and the external capacitor to prevent high frequency oscillations. C + r ta r tb fb track master 0.8v v cc r fa 2923 f05 slave r fb dc/dc + C fb out figure 5. simplified tracking cell
LTC2923 9 2923fa figure 6. simplified functional diagram the LTC2923 features an electronic circuit breaker func- tion that protects the optional series fet against short circuits. when the fet is fully enhanced (gate > ramp + 4.9v), the electronic circuit breaker is enabled. then, if the voltage across the fet (v ds ) exceeds 200mv as measured from v cc to the ramp pin for more than about 10 s the gate of the fet is pulled down with 20ma, turning it off. because the slaved supplies track the ramp pin, they are pulled low by the tracking circuit when a short-circuit fault occurs. following a short-circuit fault, the fet is latched off until the fault is cleared by pulling the on pin below 0.4v. ramp buffer the rampbuf pin provides a buffered version of the ramp pin voltage that drives the resistive dividers on the trackx pins. when there is no external fet, it provides up to 2ma to drive the resistors even though the gate pin only supplies 10 a. the rampbuf pin also proves useful in systems with an external fet. since the track cell in the simplified functional diagram above drives 0.8v on the trackx pins, if r tbx is connected directly to the fets source, the trackx pin could potentially pull up the fets source towards 0.8v when the fet is off. rampbuf blocks this path. applicatio s i for atio wu uu C + C + C + + C v cc 200mv gate q1 master slave1 slave2 c gate 1.2v on rampbuf 10 a v cc v cc v cc r onb r ona r ta1 r tb1 r ta2 r tb2 10 a ramp fb1 track1 0.8v C + fb2 track2 0.8v r fa1 r fb1 dc/dc r fa2 2923 f06 r fb2 dc/dc 1
LTC2923 10 2923fa applicatio s i for atio wu uu shutdown output in some applications it might be necessary to control the shutdown or run/ss pins of the slave supplies using the 12-lead LTC2923cde or LTC2923ide. the LTC2923 may not be able to supply the rated 1ma of current from the fb1 and fb2 pins when v cc is below 2.9v. if the slave power supplies are capable of operating at low input voltages, use the open-drain sdo output to drive the shdn or run/ss pins of the slave supplies (see figure 7). this will hold the slave supplies outputs low until the on pin is above 1.23v, v cc is above the 2.6v undervoltage lockout condition and there are no short-circuit faults latched. it pulls low again when the on pin is pulled below 1.23v and the ramp pin is below about 100mv. when two supplies must have their run/ss or shdn pins controlled indepen- dently, tie a schottky diode between each pin and the sdo output (see figure 8). status output the status pin provides an indication that the supplies are finished ramping up. this pin is an open-drain output that pulls low until the gate has been fully charged. since the gate pin drives the gate of the external fet, or the ramp pin directly when no fet is used, the supplies are completely ramped up when the gate pin is fully charged. it will go low again when the gate pin is pulled low, either because of a short-circuit fault or because the on pin has been pulled low. q1 c gate 10nf 0.1 f 10 ? r status 10k v cc v in v in v in r onb 138k v in 3.3v r tb1 16.5k r tb2 887k r fa1 35.7k 1.8v 3.3v r fb1 16.5k r ta2 412k r ta1 13k r ona 100k rampbuf track1 track2 fb1 gate LTC2923 gnd 2923 f07 ramp r fa2 412k 2.5v r fb2 887k dc/dc in fb = 1.235v out dc/dc in fb = 0.8v run/ss run/ss out fb2 sdo status on q1 c gate 10nf r status 10k v cc v in v in v in r onb 138k v in 3.3v r tb1 16.5k r tb2 887k r fa1 35.7k 1.8v 3.3v r fb1 16.5k r ta2 412k r ta1 13k r ona 100k rampbuf track1 track2 fb1 gate LTC2923 gnd 2923 f08 ramp r fa2 412k 2.5v r fb2 887k dc/dc in fb = 1.235v out dc/dc in fb = 0.8v run/ss run/ss out fb2 sdo status on 0.1 f 10 ? figure 7 figure 8
LTC2923 11 2923fa applicatio s i for atio wu uu 3-step design procedure the following 3-step procedure allows one to complete a design for any of the tracking or sequencing profiles shown in figures 1 to 4. a basic three supply application circuit is shown in figure 9. 1. set the ramp rate of the master signal . solve for the value of c gate , the capacitor on the gate pin, based on the desired ramp rate (v/s) of the master supply, s m . c i s a gate gate m = where i gate 10 (1) if the external fet has a gate capacitance comparable to c gate , then the external capacitors value should be reduced to compensate for the fets gate capacitance. if no external fet is used, tie the gate and ramp pins together. 2. solve for the pair of resistors that provide the desired ramp rate of the slave supply, assuming no delay . choose a ramp rate for the slave supply, s s . if the slave supply ramps up coincident with the master supply or with a fixed voltage offset, then the ramp rate equals the master supplys ramp rate. be sure to use a fast enough ramp rate for the slave supply so that it will finish ramping before the master supply has reached its final supply value. if not, the slave supply will be held below the intended regulation value by the master supply. use the following formulas to determine the resistor values for the desired ramp rate, where r fb and r fa are the feedback resistors in the slave supply and v fb is the feedback reference voltage of the slave supply: rr s s tb fb m s = ? (2) r v v r v r v r ta track fb fb fb fa track tb = + C (3) where v track 0.8v. note that large ratios of slave ramp rate to master ramp rate, s s /s m , may result in negative values for r ta . if sufficiently large delay is used in step 3, r ta will be positive, otherwise s s /s m must be reduced. 3. choose r ta to obtain the desired delay . if no delay is required, such as in coincident and ratiometric tracking, then simply set r ta = r ta . if a delay is desired, as in offset tracking and supply se- quencing, calculate r ta to determine the value of r ta where t d is the desired delay in seconds. r vr ts ta track tb dm = ? ? (4) r ta = r ta ||r ta (5) the parallel combination of r ta and r ta as noted in step 2, small delays and large ratios of slave ramp rate to master ramp rate (usually only seen in sequencing) may result in solutions with negative values for r ta . in such cases, either the delay must be increased or the ratio of slave ramp rate to master ramp rate must be reduced. figure 9. three supply application q1 c gate v cc r onb v in r tb1 r tb2 r fa1 slave1 master r fb1 r ta2 r ta1 r ona on fb1 gate LTC2923 gnd 2923 f09 ramp r fa2 slave2 r fb2 rampbuf track1 track2 fb2 dc/dc in v in v in fb out dc/dc in fb out 0.1 f 10 ?
LTC2923 12 2923fa in this example, all supplies remain low while the on pin is held below 1.23v. when the on pin rises above 1.23v, 10 a pulls up c gate and the gate of the fet at 1000v/s. as the gate of the fet rises, the source follows and pulls up the output to 3.3v at 1000v/s. this output serves as the master signal and is buffered from the ramp pin to the rampbuf pin. as this output and the rampbuf pin rise, the current from the track pins is reduced. conse- quently, the voltage at the slave supplys outputs in- creases, and the slave supplies track the master supply. when the on pin is again pulled below 1.23v, 10 a will pull down c gate and the gate of the fet at 1000v/s. if the loads on the outputs are sufficient, all outputs will track down coincidently at 1000v/s. applicatio s i for atio wu uu coincident tracking example 1ms/div 2923 f10b 1v/div 1ms/div 2923 f10a 1v/div figure 10. coincident tracking (from figure 11) master slave2 slave1 figure 11. coincident tracking example a typical three supply application is shown in figure 11. the master signal is a 3.3v module. the slave 1 supply is a 1.8v switching power supply and the slave 2 supply is a 2.5v switching power supply. both slave supplies track coinci- dently with the 3.3v supply that is controlled with an ex- ternal fet. the ramp rate of the supplies is 1000v/s. the 3-step design procedure detailed previously can be used to determine component values. only the slave 1 supply is considered here as the procedure is the same for the slave 2 supply. 1. set the ramp rate of the master signal. from equation 1: c a vs nf gate = = 10 1000 10 / 2. solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay. from equation 2: rk vs vs k tb = ? = ? 16 5 1000 1000 16 5 .? / / . from equation 3: r v v k v k v k k ta = ? + ?? ? 08 1 235 16 5 1 235 35 7 08 16 5 13 . . . . . C . . 3. choose r ta to obtain the desired delay. since no delay is desired, r ta = r ta q1 c gate 10nf v cc r onb 138k 3.3v r tb1 16.5k r tb2 887k r fa1 35.7k 1.8v slave1 3.3v master r fb1 16.5k r ta2 412k r ta1 13k r ona 100k on fb1 gate LTC2923 gnd 2923 f11 ramp r fa2 412k 2.5v slave2 r fb2 887k rampbuf track1 track2 fb2 dc/dc in 3.3v 3.3v fb = 1.235v out dc/dc in fb = 0.8v out 0.1 f 10 ?
LTC2923 13 2923fa applicatio s i for atio wu uu ratiometric tracking example figure 13. ratiometric tracking example this example converts the coincident tracking example to the ratiometric tracking profile shown in figure 12, using two supplies without an external fet. the ramp rate of the master signal remains unchanged (step 1) and there is no delay in ratiometric tracking (step 3), so only the result of step 2 in the 3-step design procedure needs to be consid- ered. in this example, the ramp rate of the 1.8v slave 1 supply ramps up at 600v/s and the 2.5v slave 2 supply ramps up at 850v/s. always verify that the chosen ramp rate will allow the supplies to ramp-up completely before rampbuf reaches v cc . if the 1.8v supply were to ramp- up at 500v/s it would only reach 1.65v because the rampbuf signal would reach its final value of v cc = 3.3v before the slave supply reached 1.8v. 2. solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay . from equation 2: rk vs vs k tb = ?? 16 5 1000 600 27 4 .? / / . from equation 3: r v v k v k v k k ta = ? + ?? = ? 08 1 235 16 5 1 235 35 7 08 27 5 10 . . . . . C . . step 3 is unnecessary because there is no delay, so r ta = r ta . 1ms/div 2923 f12b 1v/div 1ms/div 2923 f12a 1v/div figure 12. ratiometric tracking (from figure 13) slave2 slave1 c gate 10nf 0.1 f v cc r onb 138k 3.3v r tb1 27.4k r tb2 1m r fa1 35.7k 1.8v slave1 r fb1 16.5k r ta2 383k r ta1 10k r ona 100k on fb1 gate LTC2923 gnd 2923 f13 ramp r fa2 412k 2.5v slave2 r fb2 887k rampbuf track1 track2 fb2 dc/dc in 3.3v 3.3v fb = 1.235v out dc/dc in fb = 0.8v out
LTC2923 14 2923fa offset tracking example applicatio s i for atio wu uu figure 15. offset tracking example converting the circuit in the coincident tracking example to the offset tracking shown in figure 14 is relatively simple. here the 1.8v slave 1 supply ramps up 1v below the master. the ramp rate remains the same (1000v/s), so there are no changes necessary to steps 1 and 2 of the 3-step design procedure. only step 3 must be considered. be sure to verify that the chosen voltage offsets will allow the slave supplies to ramp up completely. in this example, if the voltage offset were 2v, the slave supply would only ramp up to 3.3v C 2v = 1.3v. 3. choose r ta to obtain the desired delay. first, convert the desired voltage offset, v os , to a delay, t d , using the ramp rate: t v s v vs ms d os s == = 1 1000 1 / (6) from equation 4: r vk ms v s k ta = ? = ? 0 8 16 5 1 1000 13 2 .?. ?/ . from equation 5: r ta = 13.1k ? ||13.2k ? 6.65k ? 1ms/div 2923 f14b 1v/div 1ms/div 2923 f14a 1v/div figure 14. offset tracking (from figure 15) slave2 slave1 master q1 c gate 10nf v cc r onb 138k 3.3v r tb1 16.5k r tb2 887k r fa1 35.7k 1.8v slave1 3.3v master r fb1 16.5k r ta2 316k r ta1 6.65k r ona 100k on fb1 fb2 gate LTC2923 gnd 2923 f15 ramp r fa2 412k 2.5v slave2 r fb2 887k rampbuf track1 track2 dc/dc in 3.3v 3.3v fb = 1.235v out dc/dc in fb = 0.8v out 0.1 f 10 ?
LTC2923 15 2923fa supply sequencing example applicatio s i for atio wu uu figure 17. supply sequencing example in figure 16, the slave 1 supply and the slave 2 supply are sequenced instead of tracking. the 3.3v supply ramps up at 100v/s with an external fet and serves as the master signal. the 1.8v slave 1 supply ramps up at 1000v/s beginning 10ms after the master signal starts to ramp up. the 2.5v slave 2 supply ramps up at 1000v/s beginning 25ms after the master signal begins to ramp up. note that not every combination of ramp rates and delays is pos- sible. small delays and large ratios of slave ramp rate to master ramp rate may result in solutions that require negative resistors. in such cases, either the delay must be increased or the ratio of slave ramp rate to master ramp rate must be reduced. in this example, solving for the slave 1 supply yields: 1. set the ramp rate of the master signal. from equation 1: c a vs nf gate = = 10 100 100 / 2. solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay. from equation 2: rk vs vs k tb = ? = ? 16 5 100 1000 165 .? / / . 10ms/div 2923 f16b 1v/div 10ms/div 2923 f16a 1v/div figure 16. supply sequencing (from figure 17) slave2 slave1 master from equation 3: r v v k v k v k k ta = ? + ?? = ? 08 1 235 16 5 1 235 35 7 08 165 213 . . . . . C . . C. 3. choose r ta to obtain the desired delay. from equation 4: r vk ms v s k ta = ? = ? 08 165 10 100 132 .?. ?/ . from equation 5: r ta = C 2.13k ? ||1.32k ? = 3.48k ? q1 c gate 100nf v cc r onb 138k 3.3v r tb1 1.65k r tb2 88.7k r fa1 35.7k 1.8v slave1 3.3v master r fb1 16.5k r ta2 36.5k r ta1 3.48k r ona 100k on rampbuf track1 track2 fb1 gate LTC2923 gnd 2923 f17 ramp dc/dc in 3.3v 3.3v fb = 1.235v out r fa2 412k 2.5v slave2 r fb2 887k dc/dc in fb = 0.8v out fb2 0.1 f 10 ?
LTC2923 16 2923fa applicatio s i for atio wu uu final sanity checks the collection of equations below is useful for identifying unrealizable solutions. as stated in step 2, the slave supply must finish ramping before the master signal has reached its final voltage. this can be verified by the following equation: v r r v where v v track tb ta cc track 108 + ? ? ? ? ? ? <= ,. it is possible to choose resistor values that require the LTC2923 to supply more current than the electrical char- acteristics table guarantees. to avoid this condition, check that i trackx does not exceed 1ma and i rampbuf does not exceed 2ma. to confirm that i trackx < 1ma, the trackx pins maxi- mum guaranteed current, verify that: v rr ma track ta tb < 1 finally, check that the rampbuf pin will not be forced to sink more then 2ma when it is at 0v or be forced to source more than 2ma when it is at v cc . v r v r ma and v rr v rr ma track tb track tb cc ta tb cc ta tb 12 11 2 2 2 2 +< + + + < caution with boost and linear regulators note that the LTC2923s tracking cell is not able to control the outputs of all types of power supplies. if it is necessary to control one of these types of supplies, where the output is not controllable through its feedback node, the series fet can be used to control one supplys output. for example, boost regulators commonly contain an inductor and diode between the input supply and the output supply providing a dc current path when the output voltage falls below the input voltage. therefore, the LTC2923s track- ing cell will not effectively drive the supplys output below the input. special caution should be taken when considering the use of linear regulators. three-terminal linear regulators have a reference voltage that is referred to the output supply rather than to ground. in this case, driving current into the regulators feedback node will cause its output to rise rather than fall. even linear regulators that have their reference voltage referred to ground, including low drop- out regulators (ldos), may be problematic. linear regu- lators commonly contain circuitry that prevents driving their outputs below their reference voltage. this may not be obvious from the data sheets, so lab testing is recom- mended whenever the LTC2923s tracking cell is used to control linear regulators. load requirements when the supplies are ramped down quickly, either the load or the supply itself must be capable of sinking enough current to support the ramp rate. for example, if there is a large output capacitance on the supply and a weak resistive load, supplies that do not sink current will have their falling ramp rate limited by the rc time constant of the load and the output capacitance. figure 18 shows the case when the 2.5v supply does not track the 1.8v and 3.3v supplies near ground. start-up delays often power supplies do not start-up immediately when their input supplies are applied. if the LTC2923 tries to ramp-up these power supplies as soon as the input supply is present, the start-up of the outputs may be delayed, defeating the tracking circuit (figure 19). often this delay is intentionally configured by a soft-start capacitor. this can be remedied either by reducing the soft-start capacitor on the slave supply or by including a capacitor in the on pins resistive divider to delay the ramp up. see figure 20.
LTC2923 17 2923fa layout considerations be sure to place a 0.1 f bypass capacitor as near as possible to the supply pin of the LTC2923. a 10 ? resistor located near the fet and connected between the fets gate and the external c gate capacitor is recommended. this will almost assuredly eliminate the troublesome high frequency oscillations that can occur due to the fet interacting with pcb parasitics. to minimize the noise on the slave supplies outputs, keep the traces connecting the fbx pins of the LTC2923 and the feedback nodes of the slave supplies as short as possible. in addition, do not route those traces next to signals with fast transition times. in some circumstances it might be advantageous to add a resistor near the feedback node of the slave supply in series with the fbx pin of the LTC2923. this resistor must not exceed: r vv i v v rr series fb max fb fa fb == ? ? ? ? ? ? () 15 15 1 .C . C|| this resistor is most effective if there is already a capacitor at the feedback node of the slave supply (often a compen- sation component). increasing the capacitance on a slave supplys feedback node will further improve the noise immunity, but could affect the stability and transient response of the supply. applicatio s i for atio wu uu v cc out fet r fa r fb r series c gate 10 ? minimize trace length v cc LTC2923 2923 f21 ramp fb1 gate gnd 0.1 f dc/dc fb out figure 21. layout considerations master 1ms/div 2923 f18 figure 18. weak resistive load 1v/div slave2 slave1 1v/div 1ms/div 2923 f20 on slave2 slave1 master figure 20. on pin delayed figure 19. power supply start-ups delayed 1v/div 1ms/div 2923 f19 on slave2 slave1 master
LTC2923 18 2923fa ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) u package descriptio msop (ms) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C 0.27 (.007 C .011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc
LTC2923 19 2923fa u package descriptio de package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695) 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom viewexposed pad 1.70 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 0.25 0.05 3.30 0.10 (2 sides) 1 6 12 7 0.50 bsc pin 1 notch pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (ue12/de12) dfn 0603 0.25 0.05 3.30 0.05 (2 sides) recommended solder pad pitch and dimensions 1.70 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2923 20 2923fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2003 lt/tp 1104 1k rev a ?printed in usa related parts part number description comments ltc1645 dual hot swap tm controller operates from 1.2v to 12v, allows supply sequencing ltc2920 power supply margining controller single or dual versions, symmetric as symmetric high and low margining ltc2921/ltc2922 power supply tracker with input monitors includes 3 (ltc2921) or 5 (ltc2922) remote sense switches ltc2925 multiple power supply tracking controller up to 4 supplies, status and fault pins, slave supply shutdown, remote sense switch lt ? 4220 dual supply hot swap controller 2.7v to 16.5v, supply tracking mode ltc4230 triple hot swap controller with multifunction 1.7v to 16.5v, active inrush limiting, fast comparator current control ltc4253 C 48v hot swap controller and supply sequencer floating supply from C15v, active current limiting, enables three dc/dc converters hot swap is a trademark of linear technology corporation. typical applicatio s u daisy-chained application c gate 10nf v cc r onb 138k 3.3v r tb r tb r fa 1.8v slave1 r fb r ta r ta r ona 100k on fb1 gate LTC2923 gnd 2923 ta03 ramp r fa 1.5v slave2 r fb rampbuf track1 track2 fb2 dc/dc in fb = 1.235v out dc/dc in fb = 0.8v out v cc 0.1 f 0.1 f 3.3v r tb1 r tb2 r fa1 3.3v slave1 r fb1 r ta2 r ta1 on fb1 gate LTC2923 gnd ramp r fa2 2.5v slave2 r fb2 rampbuf track1 track2 fb2 dc/dc in fb = 1.235v out dc/dc in fb = 0.8v out high voltage supply application c gate 10nf v cc r onb 138k 3.3v r tb1 r tb2 r fa1 12v slave1 r fb1 r ta2 r ta1 r ona 100k on fb1 gate LTC2923 gnd 2923 ta04 ramp r fa2 5v slave2 r fb2 rampbuf track1 track2 fb2 dc/dc in fb = 1.235v out dc/dc in fb = 0.8v out 0.1 f

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